1. Technical Field
The present invention relates to a method of laying out a semiconductor integrated circuit (IC).
2. Description of the Related Art
Due to the miniaturization of semiconductor integrated circuits, the prevention of noise in semiconductor integrated circuits has become increasingly important. By inserting a decoupling capacitor into a power circuit of an integrated circuit (e.g., power routing and ground routing), the electric potential of the power circuit can be stabilized, the integrated circuit can operate in a stable manner, and the properties of the integrated circuit can be improved. Hereinafter, the term “decoupling capacitor” may be used interchangeably with the term “power capacitor.”
To design a semiconductor integrated circuit, a chip layout is determined first. In particular, input/output blocks are arranged, and functional blocks (such as analog signal circuit blocks, a core, or the like) are arranged. Wiring is arranged between the input/output blocks and the analog signal circuit blocks. Since wiring transferring an analog signal needs to be arranged according to noise reduction or impedance matching, the wiring can be manually arranged. Unit cells including a logic circuit (such as an NAND gate, a NOR gate, a flip-flop, etc.) are arranged between the functional blocks. Wiring between the unit cells, between the input/output block and the functional blocks, and between the functional block and the unit cells is also designed. The arrangement and wiring operation of a layout pattern of the integrated circuit chip are performed in a similar manner.
When a power capacitor is to be inserted, a chip layout is initially determined, and the power capacitor is then manually inserted into a predetermined space. Typically, the power capacitor and power wiring can be manually connected. In particular, a capacitor is inserted in spaces which do not belong to the input/output block and the functional block (between the input/output block and the functional block as well as between functional blocks). The capacitor and the power wiring are connected, and an integrated circuit chip layout pattern is subsequently completed.
However, since the input/output block and the functional block are arranged first during the design of a semiconductor integrated circuit, the shape or size of a space in which a capacitor is to be inserted may not match the dimensions of the capacitor. As a result, a relatively long period of time is needed to arrange the capacitor in the space so as to achieve a large capacity. In addition, increased skill may be required to arrange the elements, since the capacitance of a capacitor can vary according to a designer.